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this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 1 en29sl160 rev. g, issue date: 2008 / 09 / 09 features ? single power supply operation - full voltage range:1.65 -2.2 volt for read and write operations. - regulated voltage range: 1.8-2.2 volt read and write operations ? high performance - access times as fast as 90 ns ? low power consumption (typical values at 5 mhz) - 7 ma typical active read current - 15 ma typical program/erase current - 0.2 a typical standby current ? flexible sector architecture: - eight 8-kbyte and thirty-one 64-kbyte sectors (byte mode) - eight 4-kword and thirty-one 32-kword sectors (word mode) ? wp#/acc input pin: - write protect (wp#) function allows protection of two outermost boot sectors, regardless of sector protect status - acceleration (acc) function acceleration program timing. ? sector protection: - hardware lo cking of sectors to prevent program or erase operations within individual sectors - additionally, temporary sector unprotect allows code changes in previously locked sectors. ? high performance program/erase speed - byte/word program time: 5s/7s typical - sector erase time: 500ms typical ? jedec standard embedded erase and program algorithms ? jedec standard data # polling and toggle bits feature ? unlock bypass program command supported ? single sector and chip erase ? sector unprotect mode ? erase suspend / resume modes: read or program another sector during erase suspend mode ? low vcc write inhibit < 1.2v ? minimum 100k endurance cycle ? package options - 48-pin tsop (type 1) - 48-ball 6mm x 8mm tfbga - 48-ball 5mm x 6mm wfbga - 48-ball 5mm x 6mm wlga ? commercial and industrial temperature range general description the en29sl160 is an 16-megabit, electrically erasable, read/write non-volatile flash memory, organized as 2,097,152 bytes or 1,048,576 words. any byte can be programmed typically in 5s. the en29sl160 features 1.8v voltage read and write operation, with access time as fast as 90ns to eliminate the need for wait statements in high-performance microprocessor systems. the en29sl160 has separate output enable (oe#), chip enable (ce#), and write enable (we#) controls, which eliminate bus contention issues. this device is designed to allow either single sector or full chip erase operation, where each sector can be individually protected against program/erase operations or temporarily unprotected to erase or program. the device can sustain a minimum of 100k program/erase cycles on each sector. en29sl160 16 megabit (2048k x 8-bit / 1024k x 16-bit) flash memory boot sector flash memory, cmos 1.8 volt-only
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 2 en29sl160 rev. g, issue date: 2008 / 09 / 09 connection diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 standard tsop a15 a14 a13 a12 a11 a10 a9 a8 a19 nc we# reset# nc wp#/acc ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte# vss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 vcc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# vss ce# a0
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 3 en29sl160 rev. g, issue date: 2008 / 09 / 09 notes: 1. ry/by#, byte# are not available for wfbga package. 2. it is organized as 1m x 16 (16mbit) a6 a2 b6 a4 c6 a6 d6 a17 e6 nc f6 nc g6 we# h6 i6 a9 j6 a11 a5 a1 b5 a3 c5 a7 d5 wp #/a h5 nc i5 a10 j5 a13 k5 a14 a4 a0 b4 a5 c4 a18 i4 a8 j4 a12 k4 a15 a3 ce# b3 dq8 c3 dq10 i3 dq4 j3 dq11 k3 a16 a2 v ss b2 oe# c2 dq9 d2 a19 h2 nc i2 dq5 j2 dq6 k2 dq7 b1 dq0 c1 dq1 d1 dq2 e1 dq3 f1 v dd g1 dq12 h1 dq13 i1 dq14 j1 dq15 k1 v ss wfbga and wlga top view, balls facing down wp#/acc wp#/acc reset#
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 4 en29sl160 rev. g, issue date: 2008 / 09 / 09 table 1. pin description figure 1. logic diagram pin name function a0-a19 20 addresses dq0-dq14 15 data inputs/outputs dq15 / a-1 dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) ce# chip enable oe# output enable reset# hardware reset pin ry/by# ready/busy output we# write enable wp#/acc hardware write protect/acceleration pin vcc supply voltage (1.65-2.2v) vss ground nc not connected to anything byte# byte/word mode
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 5 en29sl160 rev. g, issue date: 2008 / 09 / 09 table 2. top boot sector address tables (en29sl160t) address range (in hexadecimal) sector a19 a18 a17 a16 a15 a14 a13 a12 sector size (kbytes/ kwords) byte mode (x8) word mode (x16) sa0 0 0 0 0 0 x x x 64/32 000000?00ffff 00000?07fff sa1 0 0 0 0 1 x x x 64/32 010000?01ffff 08000?0ffff sa2 0 0 0 1 0 x x x 64/32 020000?02ffff 10000?17fff sa3 0 0 0 1 1 x x x 64/32 030000?03ffff 18000?1ffff sa4 0 0 1 0 0 x x x 64/32 040000?04ffff 20000?27fff sa5 0 0 1 0 1 x x x 64/32 050000?05ffff 28000?2ffff sa6 0 0 1 1 0 x x x 64/32 060000?06ffff 30000?37fff sa7 0 0 1 1 1 x x x 64/32 070000?07ffff 38000?3ffff sa8 0 1 0 0 0 x x x 64/32 080000?08ffff 40000?47fff sa9 0 1 0 0 1 x x x 64/32 090000?09ffff 48000?4ffff sa10 0 1 0 1 0 x x x 64/32 0a0000?0affff 50000?57fff sa11 0 1 0 1 1 x x x 64/32 0b0000?0bffff 58000?5ffff sa12 0 1 1 0 0 x x x 64/32 0c0000?0cffff 60000?67fff sa13 0 1 1 0 1 x x x 64/32 0d0000?0dffff 68000?6ffff sa14 0 1 1 1 0 x x x 64/32 0e0000?0effff 70000?77fff sa15 0 1 1 1 1 x x x 64/32 0f0000?0fffff 78000?7ffff sa16 1 0 0 0 0 x x x 64/32 100000?10ffff 80000?87fff sa17 1 0 0 0 1 x x x 64/32 110000?11ffff 88000?8ffff sa18 1 0 0 1 0 x x x 64/32 120000?12ffff 90000?97fff sa19 1 0 0 1 1 x x x 64/32 130000?13ffff 98000?9ffff sa20 1 0 1 0 0 x x x 64/32 140000?14ffff a0000?a7fff sa21 1 0 1 0 1 x x x 64/32 150000?15ffff a8000?affff sa22 1 0 1 1 0 x x x 64/32 160000?16ffff b0000?b7fff sa23 1 0 1 1 1 x x x 64/32 170000?17ffff b8000?bffff sa24 1 1 0 0 0 x x x 64/32 180000?18ffff c0000?c7fff sa25 1 1 0 0 1 x x x 64/32 190000?19ffff c8000?cffff sa26 1 1 0 1 0 x x x 64/32 1a0000?1affff d0000?d7fff sa27 1 1 0 1 1 x x x 64/32 1b0000?1bffff d8000?dffff sa28 1 1 1 0 0 x x x 64/32 1c0000?1cffff e0000?e7fff sa29 1 1 1 0 1 x x x 64/32 1d0000?1dffff e8000?effff sa30 1 1 1 1 0 x x x 64/32 1e0000?1effff f0000?f7fff sa31 1 1 1 1 1 0 0 0 8/4 1f0000?1f1fff f8000?f8fff sa32 1 1 1 1 1 0 0 1 8/4 1f2000?1f3fff f9000?f9fff sa33 1 1 1 1 1 0 1 0 8/4 1f4000?1f5fff fa000?fafff sa34 1 1 1 1 1 0 1 1 8/4 1f6000?1f7fff fb000?fbfff sa35 1 1 1 1 1 1 0 0 8/4 1f8000?1f9fff fc000?fcfff sa36 1 1 1 1 1 1 0 1 8/4 1fa000?1fbfff fd000?fdfff sa37 1 1 1 1 1 1 1 0 8/4 1fc000?1fdfff fe000?fefff sa38 1 1 1 1 1 1 1 1 8/4 1fe000?1fffff ff000?fffff
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 6 en29sl160 rev. g, issue date: 2008 / 09 / 09 table 3. bottom boot sector address tables (en29sl160b) address range (in hexadecimal) sector a19 a18 a17 a16 a15 a14 a13 a12 sector size (kbytes/ kwords) byte mode (x8) word mode(x16) sa0 0 0 0 0 0 0 0 0 8/4 000000?001fff 00000?00fff sa1 0 0 0 0 0 0 0 1 8/4 002000?003fff 01000?01fff sa2 0 0 0 0 0 0 1 0 8/4 004000?005fff 02000?02fff sa3 0 0 0 0 0 0 1 1 8/4 006000?007fff 03000?03fff sa4 0 0 0 0 0 1 0 0 8/4 008000?009fff 04000?04fff sa5 0 0 0 0 0 1 0 1 8/4 00a000?00bfff 05000?05fff sa6 0 0 0 0 0 1 1 0 8/4 00c000?00dfff 06000?06fff sa7 0 0 0 0 0 1 1 1 8/4 00e000?00ffff 07000?07fff sa8 0 0 0 0 1 x x x 64/32 010000?01ffff 08000?0ffff sa9 0 0 0 1 0 x x x 64/32 020000?02ffff 10000?17fff sa10 0 0 0 1 1 x x x 64/32 030000?03ffff 18000?1ffff sa11 0 0 1 0 0 x x x 64/32 040000?04ffff 20000?27fff sa12 0 0 1 0 1 x x x 64/32 050000?05ffff 28000?2ffff sa13 0 0 1 1 0 x x x 64/32 060000?06ffff 30000?37fff sa14 0 0 1 1 1 x x x 64/32 070000?07ffff 38000?3ffff sa15 0 1 0 0 0 x x x 64/32 080000?08ffff 40000?47fff sa16 0 1 0 0 1 x x x 64/32 090000?09ffff 48000?4ffff sa17 0 1 0 1 0 x x x 64/32 0a0000?0affff 50000?57fff sa18 0 1 0 1 1 x x x 64/32 0b0000?0bffff 58000?5ffff sa19 0 1 1 0 0 x x x 64/32 0c0000?0cffff 60000?67fff sa20 0 1 1 0 1 x x x 64/32 0d0000?0dffff 68000?6ffff sa21 0 1 1 1 0 x x x 64/32 0e0000?0effff 70000?77fff sa22 0 1 1 1 1 x x x 64/32 0f0000?0fffff 78000?7ffff sa23 1 0 0 0 0 x x x 64/32 100000?10ffff 80000?87fff sa24 1 0 0 0 1 x x x 64/32 110000?11ffff 88000?8ffff sa25 1 0 0 1 0 x x x 64/32 120000?12ffff 90000?97fff sa26 1 0 0 1 1 x x x 64/32 130000?13ffff 98000?9ffff sa27 1 0 1 0 0 x x x 64/32 140000?14ffff a0000?a7fff sa28 1 0 1 0 1 x x x 64/32 150000?15ffff a8000?affff sa29 1 0 1 1 0 x x x 64/32 160000?16ffff b0000?b7fff sa30 1 0 1 1 1 x x x 64/32 170000?17ffff b8000?bffff sa31 1 1 0 0 0 x x x 64/32 180000?18ffff c0000?c7fff sa32 1 1 0 0 1 x x x 64/32 190000?19ffff c8000?cffff sa33 1 1 0 1 0 x x x 64/32 1a0000?1affff d0000?d7fff sa34 1 1 0 1 1 x x x 64/32 1b0000?1bffff d8000?dffff sa35 1 1 1 0 0 x x x 64/32 1c0000?1cffff e0000?e7fff sa36 1 1 1 0 1 x x x 64/32 1d0000?1dffff e8000?effff sa37 1 1 1 1 0 x x x 64/32 1e0000?1effff f0000?f7fff sa38 1 1 1 1 1 x x x 64/32 1f0000?1fffff f8000?fffff
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 7 en29sl160 rev. g, issue date: 2008 / 09 / 09 product selector guide product number en29sl160 full voltage range: vcc=1.65 ? 2.2 v -90 speed option max access time, ns ( t acc ) 90 max ce# access, ns ( t ce ) 90 max oe# access, ns ( t oe ) 35 block diagram
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 8 en29sl160 rev. g, issue date: 2008 / 09 / 09 table 3. operating modes 16m flash user mode table dq8-dq15 operation ce# oe# we# reset# wp#/ acc a0-a19 (note 1) dq0- dq7 byte# = v ih byte# = v il read l l h h l / h a in d out d out high-z write l h l h (note 1) a in d in d in high-z cmos standby v cc 0.2v x x v cc 0.2v x x high-z high-z high-z output disable l h h h x x high-z high-z high-z hardware reset x x x l x x high-z high-z high-z temporary sector unprotect x x x v id (note 1) a in d in d in x sector protect (note 2) l h l v id x sector address, a6 = l, a1 = h, a0 = l d in x x sector unprotect (note 2) l h l v id (note 1) sector address, a6 = l, a1 = h, a0 = l d in x x l=logic low= v il , h=logic high= v ih , v id = v hh =10.0 1.0v, x=don?t care (either l or h, but not floating!), d in =data in, d out =data out, a in =address in, notes: 1. if wp#/acc = v il , the two outermost boot sectors are protected. if wp#/acc = v ih the outermost boot sector protection depends on whether they were last protected or unprotected. if wp#/acc = v hh , all sectors will be unprotected. 2. please refer to ? sector / sector group protection and unprotection ?, flowchart 7a and flowchart 7b. table 4. device identifi ction (autoselect codes) 16m flash manufacturer/device id table note: 1. if a manufacturing id is read with a8=l, the chip will output a configuration code 7fh. a further manufacturing id must be read with a8=h. 2. a9 = v id is for hv a9 autoselect mode only. a9 must be vcc (cmos logic level) for command autoselect mode. description mode ce # oe # w e# a19 to a12 a11 to a10 a9 2 a8 a7 a6 a5 to a2 a1 a0 dq8 to dq15 dq7 to dq0 manufacturer id: eon l l h x x v id h 1 x l x l l x 1ch word l l h 22h e4h device id (top boot block) byte l l h x x v id xxlxlh x e4h word l l h 22h e7h device id (bottom boot block) byte l l h x x v id xxlxlh x e7h x 01h (protected) sector protection verification l l h sa x v id xxlxh l x 00h (unprotected)
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 9 en29sl160 rev. g, issue date: 2008 / 09 / 09 user mode definitions word / byte configuration the signal set on the byte# pin controls whether the device data i/o pins dq15-dq0 operate in the byte or word configuration. when the byte# pin is set at logic ?1?, then the device is in word configuration, dq15-dq0 are active and are controlled by ce# and oe#. on the other hand, if the byte# pin is set at logic ?0?, then the device is in byte configuration, and only data i/o pins dq0-dq7 are active and controlled by ce# and oe#. the data i/o pins dq8- dq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. standby mode the en29sl160 has a cmos-compatible standby mode, which reduces the current to < 0.2a (typical). it is placed in cmos-compatible standby when the ce# pin is at v cc 0.2. reset# and byte# pin must also be at cmos input levels. if ce# and reset# are held at v ih , but not within v cc 0.2v, the device will be in the standby modes, but the standby current will be greater. the outputs are in a high-impedance state independent of the oe# input. read mode the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device out puts status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see ?erase suspend/erase resume commands? for more additional information. the system must issue the reset command to re-enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see the ?reset command? additional details. output disable mode when the oe# pin is at a logic high level (v ih ), the output from the en29sl260 is disabled. the output pins are placed in a high impedance state. auto select identification mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on dq15?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id ( 9.0 v to 11.0 v) on address pin a9. address pins a8, a6, a1, and a0 must be as shown in autoselect codes table. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. refer to the corresponding sector address tables. the command definitions table shows the remaining address bits that are don?t-care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq15?dq0.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 10 en29sl160 rev. g, issue date: 2008 / 09 / 09 to access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the command definitions table. this method does not require v id . see ?command definitions? for details on using the autoselect mode. write mode write operations, including programming data and erasing sectors of memory, require the host system to write a command or command sequence to the device. write cycles are initiated by placing the byte or word address on the device?s address inputs while the data to be written is input on dq[7:0] in byte mode (byte# = l) or on dq[15:0] in word mode (byte# = h). the host system must drive the ce# and we# pins low and the oe# pin high for a valid write operation to take place. all addresses are latched on the falling edge of we# and ce#, whic hever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. the system is not required to provide further controls or timings. the device automatically provides internally generated program / erase pulses and verifies the programmed /erased cells? margin. the host system can detect completion of a program or erase operation by observing the ry/by# pin, or by reading the dq[7] (data# polling) and dq[6] (toggle) status bits. the ?command definitions? section of this document provides details on the specific device commands implemented in the en29sl160. reset#: hardware reset pin the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at vss0.3 v, the device draws cmos standby current (icc2). if reset# is held at vil but not within vss0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. if reset# is asserted during a program or erase operation, the ry/by# pin will immediately go to a ?1? but the actual internal operations may be active until t ready (during embedded algorithms: 20us) amount of time has passed. the system thus must wait at least t ready amount of time after the reset# is asserted. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algorithms: 500ns). the system can read data t rh after the reset# pin returns to v ih . refer to the dc characteristics tables icc3 for reset# parameters and to the figures at page 26 on datasheet for the timing diagram. sector /sector group protection and unprotection the hardware sector protection feature disables bo th program and erase operations in any sector. the hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. there are two methods to enabling this hardware protection circuitry. the first one requires only that the reset# pin be at v id and then standard microprocessor timings can be used to enable or
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 11 en29sl160 rev. g, issue date: 2008 / 09 / 09 disable this feature. see flowchart 7a and 7b for the algorithm and figure 12 for the timings. when doing sector unprotect, all the other sectors should be protected first. the second method is meant for programming equipment. this method requires v id be applied to both oe# and a9 pin and non-standard microprocessor timings are used. this method is described in a separate document called en29sl160 supplement, which can be obtained by contacting a representative of eon silicon solution, inc. top boot sector/sector group organization table (en29sl160t) for (un)protection sector / sector group a19-a12 sector/sector group size sa 0 00000xxx 64 kbytes sa 1-sa 3 00001xxx 00010xxx 00011xxx 190 (3x64) kbytes sa 4-sa 7 001xxxxx 256 (4 x 64) kbytes sa 8-sa11 010xxxxx 256 (4 x 64) kbytes sa12-sa15 011xxxxx 256 (4 x 64) kbytes sa16-sa19 100xxxxx 256 (4 x 64) kbytes sa20-sa23 101xxxxx 256 (4 x 64) kbytes sa24-sa27 110xxxxx 256 (4 x 64) kbytes sa28-sa30 11100xxx 11101xxx 11110xxx 190 (3x64) kbytes sa31 11111000 8 kbytes sa32 11111001 8 kbytes sa33 11111010 8 kbytes sa34 11111011 8 kbytes sa35 11111100 8 kbytes sa36 11111101 8 kbytes sa37 11111110 8 kbytes sa38 11111111 8 kbytes bottom boot sector/sector gr oup organization table (en29s l160b) for (un)protection sector / sector group a19-a12 sector/sector group size sa38 11111xxx 64 kbytes sa37-sa35 11110xxx 11101xxx 11100xxx 190 (3x64) kbytes sa34-sa31 110xxxxx 256 (4 x 64) kbytes sa30-sa27 101xxxxx 256 (4 x 64) kbytes sa26-sa23 100xxxxx 256 (4 x 64) kbytes sa22-sa19 011xxxxx 256 (4 x 64) kbytes sa18-sa15 010xxxxx 256 (4 x 64) kbytes sa14-sa11 001xxxxx 256 (4 x 64) kbytes sa10-sa08 00011xxx 00010xxx 00001xxx 190 (3x64) kbytes sa 7 00000111 8 kbytes sa 6 00000110 8 kbytes sa 5 00000101 8 kbytes sa 4 00000100 8 kbytes sa 3 00000011 8 kbytes sa 2 00000010 8 kbytes sa 1 00000001 8 kbytes sa 0 00000000 8 kbytes
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 12 en29sl160 rev. g, issue date: 2008 / 09 / 09 write protect / accelerated program (wp# / acc) the wp#/acc pin provides two functions. the write protect (wp#) function provides a hardware method of protecting the outermost two 8k-byte boot sector. the acc function allows faster manufacturing throughput at the factory, using an external high voltage. when wp#/acc is low, the device protects the outermost two 8k-byte boot sector; no matter the sectors are protected or unprotected using the method described in ?sector/sector group protection & chip unprotection?, program and erase operations in these sectors are ignored. when wp#/acc is high, the device reverts to the previous protection status of the outermost two 8k-byte boot sector. program and erase operations can now modify the data in the two outermost 8k-byte boot sector unless the sector is protected using sector protection. when wp#/acc is raised to v hh the memory automatically enters the unlock bypass mode(please refer to ?command definitions?), temporarily unprotects every pr otected sectors, and reduces the time required for program operation. the system would use a two-cycle program command sequence as required by the unlock bypass mode. when wp#/acc returns to v ih or v il , normal operation resumes. the transitions from v ih or v il to v hh and from v hh to v ih or v il must be slower than t b vhh b , see figure 11. note that the wp#/acc pin must not be left floating or unconnected. in addition, wp#/acc pin must not be at v hh for operations other than accelerated programming. it could cause the device to be damaged. never raise this pin to v hh from any mode except read mode, otherwise the memory may be left in an indeterminate state. a 0.1f capacitor should be connected between the wp#/acc pin and the vss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during unlock bypass program. temporary sector unprotect this feature allows temporary unprotection of previously protected sector groups to change data while in-system. the sector unprotect mode is activated by setting the reset# pin to v id . during this mode, formerly protected sectors can be programmed or erased by simply selecting the sector addresses. once is removed from the reset# pin, all the previously protected sectors are protected again. see accompanying figure and timing diagrams for more details. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30ns. the automatic sleep mode is independent of the ce#, we# and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output is latched and always available to the system. icc 5 in the dc characteristics table represents the automatic sleep mode current specification. start reset#=v id (note 1) perform erase or program operations reset#=v ih temporary sector unprotect completed ( note 2 ) notes: 1. all protected sectors unprotected. 2. previously protected sectors protected again.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 13 en29sl160 rev. g, issue date: 2008 / 09 / 09 hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the command definitions table. additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during vcc power up and power down transitions, or from system noise. low v cc write inhibit when vcc is less than v lko , the device does not accept any write cycles. this protects data during vcc power up and power down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until vcc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when vcc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih , or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. if ce#, we#, and oe# are all logical zero (not recommended usage), it will be considered a read. power-up write inhibit during power-up, the device automatically resets to read mode and locks out write cycles. even with ce# = v il , we# = v il and oe# = v ih , the device will not accept commands on the rising edge of we#.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 14 en29sl160 rev. g, issue date: 2008 / 09 / 09 command definitions the operations of en29sl160 are selected by one or more commands written into the command register to perform read/reset memory, read id, read sector protection, program, sector erase, chip erase, erase suspend and erase resume. commands are made up of data sequences written at specific addresses via the command register. the sequences for the specified operation are defined in the command definitions table (table 5). incorrect addresses, incorrect data values or improper sequences will reset the device to read mode. table 5. en29sl160 command definitions bus cycles 1 st cycle 2 nd cycle 3 rd cycle 4 th cycle 5 th cycle 6 th cycle command sequence cycles addr data addr data addr data addr data addr data addr data read 1 ra rd reset 1 xxx f0 000 7f word 555 2aa 555 100 1c 000 7f manufacturer id byte 4 aaa aa 555 55 aaa 90 200 1c word 555 2aa 555 x01 22e4 device id top boot byte 4 aaa aa 555 55 aaa 90 x02 e4 word 555 2aa 555 x01 22e7 device id bottom boot byte 4 aaa aa 555 55 aaa 90 x02 e7 xx00 word 555 2aa 555 (sa) x02 xx01 00 autoselect sector protect verify byte 4 aaa aa 555 55 aaa 90 (sa) x04 01 word 555 2aa 555 program byte 4 aaa aa 555 55 aaa a0 pa pd word 555 2aa 555 unlock bypass byte 3 aaa aa 555 55 aaa 20 unlock bypass program 2 xxx a0 pa pd unlock bypass reset 2 xxx 90 xxx 00 word 555 2aa 555 555 2aa 555 chip erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 word 555 2aa 555 555 2aa sector erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 erase suspend 1 xxx b0 erase resume 1 xxx 30 address and data values indicated in hex ra = read address: address of the memory location to be read. this is a read cycle. rd = read data: data read from location ra during read operation. this is a read cycle. pa = program address: address of the memory location to be programmed. x = don?t-care pd = program data: data to be programmed at location pa sa = sector address: address of the sector to be erased or verified. address bits a19-a12 uniquely select any sector. reading array data the device is automatically set to reading array data after power up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. following an erase suspend command, erase suspend mode is entered. the system can read array data using the standard read timings, with the only difference in that if it reads at an address within erase suspended sectors, the device outputs status data. after completing a programming
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 15 en29sl160 rev. g, issue date: 2008 / 09 / 09 operation in the erase suspend mode, the system may once again read array data with the same exception. the reset command must be issued to re-enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see next section for details on reset. reset command writing the reset command to the device resets the device to reading array data. address bits are don?t-care for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if dq5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. the command definitions table shows the address and data requirements. this is an alternative to the method that requires v id on address bit a9 and is intended for prom programmers. two unlock cycles followed by the autoselect command initiate the autoselect command sequence. autoselect mode is then entered and the system may read at addresses shown in table 4 any number of times, without needing another command sequence. the system must write the reset command to exit the autoselect mode and return to reading array data. word / byte programming command the device may be programmed by byte or by word, depending on the state of the byte# pin. programming the en29sl160 is performed by using a four bus-cycle operation (two unlock write cycles followed by the program setup command and program data write cycle). when the program command is executed, no additional cpu controls or timings are necessary. an internal timer terminates the program operation automatically. address is latched on the falling edge of ce# or we#, whichever is last; data is latched on the risi ng edge of ce# or we#, whichever is first. programming status may be checked by sampling data on dq7 (data# polling) or on dq6 (toggle bit). when the program operation is successfully completed, the device returns to read mode and the user can read the data programmed to the device at that address. note that data can not be programmed from a 0 to a 1. only an erase operation can change a data from 0 to 1. when programming time limit is exce eded, dq5 will produce a logica l ?1? and a reset command can return the device to read mode.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 16 en29sl160 rev. g, issue date: 2008 / 09 / 09 unlock bypass to speed up programming operation, the unlock bypass command may be used. once this feature is activated, the shorter two-cycle unlock bypass program command can be used instead of the normal four-cycle program command to program the device. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset command can be accepted. this mode is exited after issuing the unlock bypass reset command. the device powers up with this feature disabled the device provides accelerated program operations through the wp#/acc pin. when wp#/acc is asserted to v b hh b , the device automatically enters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. chip erase command chip erase is a six-bus-cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the command definitions table shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embedded chip erase algorithm are ignored. the system can determine the status of the erase operation by using dq7, dq6, or dq2. see ?write operation status? for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. flowchart 4 illustrates the algorithm for the eras e operation. see the erase/program operations tables in ?ac characteristics? for parameters, and to the chip/sector erase operation timings for timing waveforms. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. the command definitions table shows the address and data requirements for the sector erase command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, or dq2. refer to ?write operation status? for information on these status bits. flowchart 4 illustrates the algorithm for the erase op eration. refer to the er ase/program operations tables in the ?ac characteristics? section for parameters, and to the sector erase operations timing diagram for timing waveforms. erase suspend / resume command the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation. the erase suspend command is ignored if written during the chip
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 17 en29sl160 rev. g, issue date: 2008 / 09 / 09 erase operation or embedded program algorithm. addresses are don?t-cares when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase-suspended sectors produces status data on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. see ?write operation status? for information on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see ?write operation status? for more information. the autoselect command is not supported during erase suspend mode. the system must write the erase resume command (address bits are don?t-care) to exit the erase suspend mode and continue the sector erase operat ion. further writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasing. write operation status dq7: data# polling the en29sl160 provides da ta# polling on dq7 to indicate the st atus of the embedded operations. the data# polling feature is active during the em bedded programming, sector erase, chip erase, and erase suspend. (see table 6) when the embedded programmi ng is in progress, an attempt to read the device will produce the complement of the data last written to dq7. upon the completion of the embedded programming, an attempt to read the device will produce the true data writ ten to dq7. for the embedded programming, data# polling is valid after the risin g edge of the fourth we# or ce# pulse in the four-cycle sequence. when the embedded erase is in progress, an attemp t to read the device will produce a ?0? at the dq7 output. upon the completion of the embedded erase, the device will produce the ?1? at the dq7 output during the read cycles. for chip erase, the data# pollin g is valid after the rising edge of the sixth we# or ce# pulse in the six-cycle sequence. da ta# polling is valid after the last rising edge of the we# or ce# pulse for chip erase or sector erase. data# polling must be per formed at any address within a se ctor that is being programmed or erased and not a protected sector. otherwise, data # polling may give an ina ccurate result if the address used is in a protected sector. just prior to the completion of the embedded operations, dq7 may change asynchronously when the output enable (oe#) is low. this means that the device is driving status information on dq7 at one instant of time and valid data at the next instant of time. depending on when the system samples the dq7 output, it may read the status of valid data. even if the device has completed the embedded operations and dq7 has a valid data, the data output on dq0-dq6 may be still invalid. the valid data on dq0-dq7 will be re ad on the subsequent read attempts. the flowchart for data# polling (d q7) is shown on flowchart 5. the data# polling (dq7) timing diagram is shown in figure 8.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 18 en29sl160 rev. g, issue date: 2008 / 09 / 09 ry/by#: ready/busy the ry/by# is a dedicated, open-drain output pin that indicates whether an embedded algorithm is in progress or completed. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to vcc. in the output-low period, signifying busy, the device is actively erasing or programming. this includes programming in the erase suspend mode. if the output is high, signifying the ready, the device is ready to read array data (including during the erase suspend mode), or is in the standby mode. dq6: toggle bit i the en29sl160 provides a ?toggle bit? on dq6 to indicate to the host system the status of the embedded programming and erase operations. (see table 6) during an embedded program or erase operation, successive attempts to read data from the device at any address (by active oe# or ce#) will result in dq6 toggling between ?zero? and ?one?. once the embedded program or erase op eration is completed, dq6 will stop toggling and valid data will be read on the next successive attempts. during embedded programming, the toggle bit is valid after the rising edge of the fourth we# pulse in the four-cycle sequence. during erase operation, the toggle bit is valid after the rising edge of the sixth we# pulse for sector erase or chip erase. in embedded programmi ng, if the sector being written to is protected, dq6 will toggles for about 2 s, then stop toggling without the data in the sector having changed. in sector erase or chip erase, if all selected sectors are protec ted, dq6 will toggle for about 100 s. the chip will then return to the read mode without changing data in all protected sectors. the flowchart for the toggle bit (dq6) is shown in flowchart 6. the toggle bit timing diagram is shown in figure 9 . dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1.? this is a failure condition that indicates the program or erase cycle was not successfully completed. since it is possible that dq5 can become a 1 when the device has successfully completed its operation and has returned to read mode, the user must check again to see if the dq6 is toggling after detecting a ?1? on dq5. the dq5 failure condition may appear if the system tries to program a ?1? to a location that is previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the operation has exceeded the timing limits, dq5 produces a ?1.? under both these conditions, the system must issue the reset command to return the device to reading array data. dq3: sector erase timer after writing a sector erase command sequence, the output on dq3 can be used to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) when sector erase starts, dq3 switches from ?0? to ?1.? this device does not support multiple sector erase command sequences so it is not very meaningful since it immediately shows as a ?1? after the first 30h command. future devices may support this feature.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 19 en29sl160 rev. g, issue date: 2008 / 09 / 09 dq2: erase toggle bit ii the ?toggle bit? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase- suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to the following table to compare outputs for dq2 and dq6. flowchart 6 shows the toggle bit algorithm, and the section ?dq2: toggle bit? explains the algorithm. see also the ?dq6: toggle bit i? subsection. refer to the toggle bit timings figure for the toggle bit timing diagram. the dq2 vs. dq6 figure shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to flowchart 6 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two re ad cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operat ion. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of flowchart 6). write operation status operation dq7 (note2) dq6 dq5 (note1) dq3 dq2 (note2) ry/by# embedded program algorithm dq7# toggle 0 n/a no toggle 0 standar d mode embedded erase algorithm 0 toggle 0 1 toggle 0 reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspended sector data data data data data 1 erase suspend mode erase-suspend program dq7# toggle 0 n/a n/a 0 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. see ?dq5:exceeded timing limits? for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 20 en29sl160 rev. g, issue date: 2008 / 09 / 09 table 6. status register bits dq name logic level definition ?1? erase complete or erase sector in erase suspend ?0? erase on-going dq7 program complete or data of non-erase sector during erase suspend 7 data# polling dq7# program on-going ?-1-0-1-0-1-0-1-? erase or program on-going dq6 read during erase suspend 6 toggle bit ?-1-1-1-1-1-1-1-? erase complete ?1? program or erase error 5 error bit ?0? program or erase on-going ?1? erase operation start 3 erase time bit ?0? erase timeout period on-going ?-1-0-1-0-1-0-1-? chip erase, sector erase or erase suspend on currently addressed sector. (when dq5=1, erase error due to currently addressed sector. program during erase suspend on- going at current address 2 toggle bit dq2 erase suspend read on non erase suspend sector notes: dq7 data# polling: indicates the p/e c status check duri ng program or erase, and on completion before checking bits dq5 for program or erase success. dq6 toggle bit: remains at constant level when p/e operations are complete or erase suspend is acknowledged. successive reads output complementary data on dq6 while programming or erase operation are on-going. dq5 error bit: set to ?1? if failure in programming or erase dq3 sector erase command timeout bit: operation has started. only possible command is erase suspend (es). dq2 toggle bit: indicates the erase status and allows identification of the erased sector.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 21 en29sl160 rev. g, issue date: 2008 / 09 / 09 embedded algorithms flowchart 1. embedded program start write program command sequence (shown below) data# poll device last address? programming done increment address no yes verify data? flowchart 2. embedded program command sequence see the command definitions section fo r more information on word mode. 2aah / 55h 555h / aah 555h / a0h program address / program data
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 22 en29sl160 rev. g, issue date: 2008 / 09 / 09 flowchart 3. embedded erase flowchart 4. embedded erase command sequence see the command definitions section fo r more information on word mode. chip erase sector erase 2aah/55h 555h/aah 555h/80h 2aah/55h 555h/aah 555h/10h 555h/aah 2aah/55h 555h/80h 555h/aah 2aah/55h sector address/30h start write erase command sequence data poll from system or toggle bit successfully completed erase done data =ffh? yes no
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 23 en29sl160 rev. g, issue date: 2008 / 09 / 09 flowchart 5. data# polling algorithm notes: (1)this second read is necessary in case the first read was done at the exact instant when the status data was in transition. flowchart 6. toggle bit algorithm notes: (2) this second set of reads is necessary in case the first set of reads was done at the exact instant when the status data was in transition. no yes dq6 = toggle? dq5 = 1? dq6 = toggle? no no yes yes read data twice start read data twice (2) fail pass no no dq7 = data? dq5 = 1? dq7 = data? yes yes no yes read data start read data (1) fail pass
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 24 en29sl160 rev. g, issue date: 2008 / 09 / 09 flowchart 7a. in-system sector protect flowchart start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? no temporary sector unprotect mode yes set up sector address sector protect: write 60h to sector addr with a6 = 0, a1 = 1, a0 = 0 wait 150 s verify sector protect: write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0=0 data = 01h? no plscnt = 25? increment plscnt no device failed yes protect another sector? y es reset plscnt = 1 no remove v id from reset# write reset command sector protect complete sector protect algorithm yes wait 0.4 s
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 25 en29sl160 rev. g, issue date: 2008 / 09 / 09 flowchart 7b. in-system sector unprotect flowchart start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? temporary sector unprotect mode no yes all sectors protected? yes no protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address (see diagram 7a.) set up first sector address sector unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 wait 15 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 =0 read from sector address with a6 = 1, a1 = 1, a0 = 0 data = 00h? no plscnt = 1000? no increment plscnt yes device failed last sector verified? no set up next sector address remove v id from reset# write reset command sector unprotect com p lete sector unprotect algorithm wait 0.4 s yes yes
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 26 en29sl160 rev. g, issue date: 2008 / 09 / 09 table 7. dc characteristics (t a = 0c to 70c or ? 40c to 85c; v cc = 1.65-2.2v) notes 1. byte# pin can also be gnd 0.3v. byte# and reset# pin input buffers are always enabled so that they draw power if not at full cmos supply voltages. symbol parameter test conditions min typ max unit i li input leakage current 0v v in vcc 3 a i lo output leakage current 0v v out vcc 3 a active read current (byte mode ) 12 22 ma i cc1 active read current (word mode ) ce# = v il , oe# = v ih , f=5mhz 12 22 ma i cc2 standby current ( cmos ) ce# = byte# = reset# = vcc 0.3v (note 1) 0.2 5.0 a i cc3 vcc , reset current ce# = byte# = reset# = vcc 0.3v (note 1) 0.2 5.0 a i cc4 supply current (program or erase) byte program, sector or chip erase in progress 15 30 ma i cc5 automatic sleep mode v ih = vcc 0.3 v v il = vss 0.3 v 0.2 5.0 a v il input low voltage -0.5 0.3 x vcc v v ih input high voltage 0.7 x vcc vcc + 0.3 v v ol output low voltage i ol = 2.0 ma 0.25 v output high voltage ttl i oh = -2.0 ma 0.85 x vcc v v oh output high voltage cmos i oh = -100 a, vcc ? 0.4v v v id a9 voltage (electronic signature) 9.0 10.0 11.0 v i id a9 current (electronic signature) a9 = v id 50 a v lko supply voltage (erase and program lock-out) 1.2 1.5 v
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 27 en29sl160 rev. g, issue date: 2008 / 09 / 09 test conditions test specifications test conditions -90 unit output load 1 ttl gate output load capacitance, c l 100 pf input rise and fall times 5 ns input pulse levels 0.0-2.0 v input timing measurement reference levels 1.0 v output timing measurement reference levels 1.0 v
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 28 en29sl160 rev. g, issue date: 2008 / 09 / 09 ac characteristics hardware reset (reset#) (t a = 0c to 70c or ? 40c to 85c; v cc = 1.65-2.2v) speed options unit parameter std description test setup -90 t ready reset# pin low to read or write embedded algorithms max 20 s t ready reset# pin low to read or write non embedded algorithms max 500 ns t rp reset# pulse width min 500 ns t rh reset# high time before read min 50 ns reset# timings t rh t rp t ready 0 v ry/by# ce# oe# reset# figure 1. reset timing not during embbedded t ready t rh t rp ry/by# ce# oe# reset# figure 2. reset timings during embedded
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 29 en29sl160 rev. g, issue date: 2008 / 09 / 09 ac characteristics word / byte configuration (byte#) (t a = 0c to 70c or ? 40c to 85c; v cc = 1.65-2.2v) speed unit std parameter description -90 t bcs byte# to ce# switching setup time min 0 ns t cbh ce# to byte# switching hold time min 0 ns t rbh ry/by# to byte# switching hold time min 0 ns figure 3. byte# timings for read operations figure 4. byte# timings for write operations note: switching byte# pin not allowed during embedded operations t bcs ce# oe# byte# ce# we# t cbh t bcs byte# t rbh ry/by#
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 30 en29sl160 rev. g, issue date: 2008 / 09 / 09 table 8. ac characteristics (t a = 0c to 70c or ? 40c to 85c; v cc = 1.65-2.2 v) read-only operations characteristics parameter symbols speed options jedec standard description test setup -90 unit t avav t rc read cycle time min 90 ns t avqv t acc address to output delay ce# = v il oe# = v il max 90 ns t elqv t ce chip enable to output delay oe# = v il max 90 ns t glqv t oe output enable to output delay max 35 ns t ehqz t df chip enable to output high z max 20 ns t ghqz t df output enable to output high z max 20 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns notes : for ? 90 vcc =1.65 ? 2.2v output load: 1 ttl gate and 100 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to vcc timing measurement reference level, input and output: 1.0 v figure 5. ac waveforms for read operations addresses ce# oe# we# outputs reset# ry/by# 0v output valid t rc t acc t oe t ce t oeh t oh t df high z addresses stable
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 31 en29sl160 rev. g, issue date: 2008 / 09 / 09 table 9. ac characteristics (t a = 0c to 70c or ? 40c to 85c; v cc = 1.65-2.2v) write (erase/program) operations parameter symbols speed options jedec standard description -90 unit t avav t wc write cycle time min 90 ns t avwl t as address setup time min 0 ns t wlax t ah address hold time min 45 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setuptime min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 45 ns t whdl t wph write pulse width high min 20 ns byte typ 5 s t whwh1 t whwh1 programming operation word typ 7 s t whwh2 t whwh2 sector erase operation typ 0.5 s
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 32 en29sl160 rev. g, issue date: 2008 / 09 / 09 table 10. ac characteristics (t a = 0c to 70c or ? 40c to 85c; v cc = 1.65-2.2v) write (erase/program) operations alternate ce# controlled writes parameter symbols speed options jedec standard description -90 unit t avav t wc write cycle time min 90 ns t avel t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghel t ghel read recovery time before write (oe# high to ce# low) min 0 ns t wlel t ws we# setuptime min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 45 ns t ehel t cph ce# pulse width high min 20 ns byte typ 5 s t whwh1 t whwh1 programming operation word typ 7 s t whwh2 t whwh2 sector erase operation typ 0.5 s
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 33 en29sl160 rev. g, issue date: 2008 / 09 / 09 table 11. erase and programming performance limits parameter typ max unit comments sector erase time 0.5 10 sec chip erase time 17.5 sec excludes 00h programming prior to erasure byte programming time 5 300 s word programming time 7 300 s byte 10.6 32 chip programming time word 7.4 11 sec excludes system level overhead erase/program endurance 100k cycles minimum 100k cycles table 12. latch up characteristics parameter description min max input voltage with respect to v ss on all pins except i/o pins (including a9, reset# and oe#) -1.0 v 12.0 v input voltage with respect to v ss on all i/o pins -1.0 v vcc + 1.0 v vcc current -100 ma 100 ma note : these are latch up characteristics and the devic e should never be put under these conditions. refer to absolute maximum ratings for the actual operating limits. table 14. 48-pin tsop pin capacitance @ 25c, 1.0mhz ( v cc = 1.65-2.2v) parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf table 15. data retention parameter description test conditions min unit 150c 10 years minimum pattern data retention time 125c 20 years
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 34 en29sl160 rev. g, issue date: 2008 / 09 / 09 ac characteristics figure 6. ac waveforms for chip/sector erase operations timings notes: 1. sa=sector address (for sector erase) , va=valid address for reading status, d out =true data at read address. 2. v cc shown only to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. t dh t ds t busy t wph t ch t wp t cs t vcs t rb t wc t as t ah t ghwl t whwh2 0x2aa sa va va 0x55 0x30 status d out addresses ce# oe# we# data ry/by# v cc 0x555 for chip erase erase command sequence (last 2 cycles) read status data (last two cycles)
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 35 en29sl160 rev. g, issue date: 2008 / 09 / 09 figure 7. program operation timings notes: 1. pa=program address, pd=program data, d out is the true data at the program address. 2. v cc shown in order to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. t vcs t dh t rb t whwh1 t busy t ds t cs t wph t ch t wp t ghwl t wc t as t ah 0x555 pa pa pa pd status d out oxa0 addresses ce# oe# we# data ry/by# v cc program command sequence (last 2 cycles) program command sequence (last 2 cycles)
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 36 en29sl160 rev. g, issue date: 2008 / 09 / 09 figure 8. ac waveforms for /data polling during embedded algorithm operations notes: 1. va=valid address for reading data# polling status data 2. this diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cy cle. figure 9. ac waveforms for toggle bit during embedded algorithm operations t oeh t df t oh t busy t oe complement status data comple- ment true true status data valid data valid data t ce t acc t ch t rc va va va addresses ce# oe# we# dq[7] dq[6:0] ry/by# t rc t acc t ce t oe t oeh t ch t df t oh t busy va va va va valid status valid status valid status valid data (first read) (second d) (stops toggling) addresses ce# oe# we# dq6, dq2 ry/by#
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 37 en29sl160 rev. g, issue date: 2008 / 09 / 09 figure 10. alternate ce# controlled write operation timings notes: pa = address of the memory location to be programmed. pd = data to be programmed at byte address. va = valid address for reading program or erase status d out = array data read at va shown above are the last two cycles of the program or erase command sequence and the last status read cycle reset# shown to illustrate t rh measurement references. it cannot occur as shown during a valid command sequence. figure 11. dq2 vs. dq6 we# dq6 dq2 enter embedded erase erase suspend enter erase suspend program erase resume erase enter suspend read enter suspend program erase erase complete erase suspend read t wc t rh t as t ah t wh t ghel t cph t cp t ws t dh t ds t busy t cwhwh1 / t cwhwh2 status d out 0xa0 for program pd for program 0x30 for sector erase 0x10 for chip erase va addresses we# oe# ce# data ry/by# reset# pa for program sa for sector erase 0x555 for chip erase 0x555 for program 0x2aa for erase
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 38 en29sl160 rev. g, issue date: 2008 / 09 / 09 figure 12. sector protect/unprotect timing diagram notes: use standard microprocessor timings for this device for read and write cycles. for sector protect, use a6=0, a1=1, a0=0. for sector unprotect, use a6=1, a1=1, a0=0. temporary sector unprotect speed option unit parameter std description -90 t vidr v id rise and fall time min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s figure 13. temporary sector unprotect timing diagram v id sa, a6,a1,a0 reset# 0 v t vidr t vidr >1
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 39 en29sl160 rev. g, issue date: 2008 / 09 / 09 write protect / accelerated program figure 14. accelerated program timing diagram
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 40 en29sl160 rev. g, issue date: 2008 / 09 / 09 figure 15. 48l tsop 12mm x 20mm package outline
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 41 en29sl160 rev. g, issue date: 2008 / 09 / 09 figure 16. 48l tfbga 6mm x 8mm package outline min. nor max a - - - - - - 1.30 a1 0.23 0.29 - - - a2 0.84 0.91 - - - d 7.90 8.00 8.10 e 5.90 6.00 6.10 d1 - - - 5.60 - - - e1 - - - 4.00 - - - e - - - 0.80 - - - b 0.35 0.40 0.45 dimension in mm symbol note : 1. coplanarity: 0.1 mm
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 42 en29sl160 rev. g, issue date: 2008 / 09 / 09 figure 17. 48l wfbga 5mm x 6mm package outline min. nor max a - - - - - - 0.73 a1 0.16 0.21 0.26 a2 - - - 0.436 - - - d 4.90 5.00 5.10 e 5.90 6.00 6.10 d1 - - - 2.50 - - - e1 - - - 5.00 - - - e - - - 0.50 - - - ?b 0.27 0.32 0.37 note : 1. coplanarity: 0.1 mm dimension in mm symbol
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 43 en29sl160 rev. g, issue date: 2008 / 09 / 09 figure 18. 48l wlga 5mm x 6mm package outline min. nor max a - - - - - - 0.535 a1 0.02 0.05 0.08 d 4.90 5.00 5.10 e 5.90 6.00 6.10 d1 - - - 2.50 - - - e1 - - - 5.00 - - - e - - - 0.50 - - - ?b 0.20 0.25 0.30 note : 1. coplanarity: 0.06 mm dimension in mm symbol
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 44 en29sl160 rev. g, issue date: 2008 / 09 / 09 absolute maximum ratings parameter value unit storage temperature -65 to +125 c plastic packages -65 to +125 c ambient temperature with power applied -55 to +125 c output short circuit current 1 200 ma a9, oe#, reset# and wp#/acc 2 -0.5 to +11.5 v all other pins 3 -0.5 to vcc+0.5 v voltage with respect to ground vcc -0.5 to +4.0 v notes: 1. no more than one output shorted at a time. duration of the short circuit should not be greater than one second. 2. minimum dc input voltage on a9, oe#, reset# and wp#/acc pins is ?0.5v. during voltage transitions, a9, oe#, reset# and wp#/acc pins may undershoot v ss to ?1.0v for periods of up to 50ns and to ?2.0v for periods of up to 20ns. see figure below. maximum dc input voltage on a9, oe#, and reset# is 11.5v which may overshoot to 12.5v for periods up to 20ns. 3. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, inputs may undershoot v ss to ?1.0v for periods of up to 50ns and to ?2.0 v for periods of up to 20ns. see figure below. maximum dc voltage on output and i/o pins is v cc + 0.5 v. during voltage transitions, outputs may overshoot to v cc + 1.5 v for periods up to 20ns. see figure below. 4. stresses above the values so mentioned above may cause perma nent damage to the device. these values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability. recommended operating ranges 1 parameter value unit ambient operating temperature commercial devices industrial devices 0 to 70 -40 to 85 c regulated:2.0 to 2.2 operating supply voltage vcc full: 1.65 to 2.2 v 1. recommended operating ranges define those limits between which the functionality of the device is guaranteed. vcc +2.0v maximum negative overshoot waveform maximum positive ov ershoot waveform 0 0
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 45 en29sl160 rev. g, issue date: 2008 / 09 / 09 ordering information en29sl160 t - 90 t c p packaging content (blank) = conventional p = pb free temperature range c = commercial (0 c to +70 c) i = industrial (-40 c to +85 c) package t = 48-pin tsop b = 48-ball thin fine pitch ball grid array (tfbga) 0.80mm pitch, 6mm x 8mm package m = 48-ball very-very-thin-profile fine pitch ball grid array (wfbga) 0.50mm pitch, 5mm x 6mm package k = 48-ball very-very-thin- profile fine pitch land grid array (wlg a) speed 90 = 90ns boot code sector architecture t = top sector b = bottom sector base part number en = eon silicon solution inc. 29sl = flash, 1.8v read program erase 160 = 16 megabit (2m x 8 / 1m x 16)
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 46 en29sl160 rev. g, issue date: 2008 / 09 / 09 revisions list revision no description date a initial release 2005/12/15 b 1. change boot sector to eight 8kbyte sector at page 1,4,5 2. change i cc1 read current from 7 / 15ma to 12 / 22ma for typical and maximum condition 3. remove 70ns products at page 40 2006/10/25 c 1. add wfbga and wlga package 2007/9/21 d 1. modify sector group organization table for (un) protection in page 11 2. add write protect / accelerated program (wp# / acc) function in page 12. 3. correct the typo at table 9,10 in page 31,32 for t whwh1 from max. to typ. 4. correct the byte programming time (typ.) from 8 to 5 and word programming time (typ.) from 8 to 7 at table 11 erase and programming performance in page 33. 2007/11/15 e correct the density configuration in ordering information, in page 45 2008/03/04 f change the fbga 48 ball package thickness from 1.31mm to 1.30mm in page 41 2008/07/07 g modify wfbga and wlga package ball h6 from nc to reset# in page 3 2008/09/09

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